The present invention relates to a method of manufacturing a semiconductor device, which can be used appropriately as, e.g., a method of manufacturing a semiconductor device including a semiconductor element formed in a semiconductor substrate.
A semiconductor device having a memory cell region, and a peripheral circuit region is widely used. In the memory cell region, a memory cell such as, e.g., a nonvolatile memory or the like is formed over a semiconductor substrate. In the peripheral circuit region, a peripheral circuit made of, e.g., a MISFET (Metal Insulator Semiconductor Field Effect Transistor) or the like is formed over the semiconductor substrate.
For example, there is a case where, as a nonvolatile memory, a split-gate memory cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film is formed. At this time, the memory cell is formed of two MISFETs which are a control transistor having a control gate electrode and a memory transistor having a memory gate electrode.
When the gate electrodes of such MISFETs are formed by dry etching, the surface roughness of the side surfaces of the gate electrode may increase to locally vary the gate length.
Japanese Unexamined Patent Publication No. 2010-10475 (Patent Document 1) discloses a technique in which, in a method of manufacturing a semiconductor device, a gate electrode having line edge roughness is formed over an active region and, by oblique ion implantation from two directions inclined in the gate electrode width direction relative to the direction of a normal to a substrate, parts of the recessed portions of the roughness are kept from being subjected to the ion implantation.